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Data Sheet
Table 81. Register 0xFE13—PWM2 Falling Edge Setting (PWM2 Pin)
ADP1047/ADP1048
Bits
[7:4]
[3:2]
Bit Name
RSVD
t 2
R/W
R
R/W
Description
Reserved.
These bits contain the two LSBs of the 10-bit t 2 time. This value is always used with the eight
bits of Register 0xFE12, which contains the eight MSBs of the t 2 time.
1
Modulate enable
R/W
1 = PWM modulation acts on the t 2 edge.
0 = no PWM modulation of the t 2 edge.
0
t 2 sign
R/W
1 = positive sign. Increase of PWM modulation moves t 2 right.
0 = negative sign. Increase of PWM modulation moves t 2 left.
PWM_SET REGISTER
Table 82. Register 0xFE14—PWM_SET
Bits
[7:5]
4
Bit Name
RSVD
ADP1048 operation
R/W
R
R/W
Description
Reserved.
Reserved for the ADP1048 only.
1 = bridgeless PFC operation.
0 = interleaved PFC operation.
3
PWM resolution
R/W
1 = 5 ns.
0 = 40 ns.
2
PWM enable
R/W
1 = disable the PWM output.
0 = enable the PWM output.
1
PWM2 enable
R/W
1 = disable the PWM2 output.
0 = enable the PWM2 output.
0
Go button
R/W
The PWM settings are updated during the transition of this bit from low to high.
PWM_LIMIT REGISTER
Table 83. Register 0xFE15—PWM_LIMI T
Bits
[7:4]
[3:0]
Bit Name
Limit minimum
on time
Limit minimum
off time
R/W
R/W
R/W
Description
These bits set the minimum on time for the PWM outputs in steps of 80 ns: 0000 = 0 ns and
1111 = 1200 ns.
These bits set the minimum off time for the PWM outputs: 0000 = 40 ns, 0001 = 80 ns, 1111 =
1200 ns.
RTD ADC OFFSET TRIM SETTING (MSB) REGISTER
This register must be unlocked for write access; see Table 61.
Table 84. Register 0xFE16—RTD ADC Offset Trim Setting (MSB)
Bits
[7:2]
1
Bit Name
RSVD
Trim polarity
R/W
R/W
R/W
Description
Reserved.
1 = negative offset trim is introduced.
0 = positive offset trim is introduced.
0
RTD ADC offset trim
R/W
This bit is the MSB of the 9-bit value that sets the amount of offset trim applied to the RTD ADC
reading. The LSBs are specified in Register 0xFE17.
RTD ADC OFFSET TRIM SETTING (LSB) REGISTER
This register must be unlocked for write access; see Table 61.
Table 85. Register 0xFE17—RTD ADC Offset Trim Setting (LSB)
Bits
[7:0]
Bit Name
RTD ADC offset trim
R/W
R/W
Description
These eight bits are the LSBs of the 9-bit value that sets the amount of offset trim applied to
the RTD ADC reading. The MSB is specified in Register 0xFE16, Bit 0.
Rev. 0 | Page 63 of 84
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